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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MCM6249/D
1M x 4 Bit Static Random Access Memory
The MCM6249 is a 4,194,304 bit static random access memory organized as 1,048,576 words of 4 bits, fabricated using high-performance silicon-gate CMOS technology. Static design eliminates the need for external clocks or timing strobes, while CMOS circuitry reduces power consumption and provides for greater reliability. The MCM6249 is equipped with chip enable (E) and output enable (G) pins, allowing for greater system flexibility and eliminating bus contention problems. Either input, when high, will force the outputs into high impedance. The MCM6249 is available in a 400 mil, 32-lead surface-mount SOJ package. * * * * * * Single 5 V 10% Power Supply Fast Access Time: 20/25/35 ns Equal Address and Chip Enable Access Time All Inputs and Outputs are TTL Compatible Three-State Outputs Power Operation: 190/175/160 mA Maximum, Active AC
MCM6249
WJ PACKAGE 400 MIL SOJ CASE 857A-02
PIN ASSIGNMENT
A7 A8 A9 A17 A6 E 1
2 3 4 5 6 7 8 9
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
A1 A0 A5 A4 A19 G DQ3 VSS VCC DQ2 A2 A16 A15 A14 A3 NC
BLOCK DIAGRAM
A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 ROW DECODER MEMORY MATRIX 1024 ROWS x 4096 COLUMNS
DQ0 VCC VSS DQ1
W A13 A18 A10 A11 A12
10 11 12 13 14 15 16
PIN NAMES
DQ0 INPUT DATA CONTROL DQ3 A18 A17 A16 A15 A14 A19 A3 A2 A1 A0 DQ0 E COLUMN I/O COLUMN DECODER A0 - A19 . . . . . . . . . . . . Address Inputs W . . . . . . . . . . . . . . . . . . . . Write Enable G . . . . . . . . . . . . . . . . . . . Output Enable E . . . . . . . . . . . . . . . . . . . . . . Chip Enable DQ0 - DQ3 . . . . . . . . Data Input/Output NC . . . . . . . . . . . . . . . . . No Connection VCC . . . . . . . . . . . . + 5 V Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . . Ground
W G
DQ3
REV 4 5/95
(c) Motorola, Inc. 1995 MOTOROLA FAST SRAM
MCM6249 1
TRUTH TABLE (X = Don't Care)
E H L L L G X H L X W X H H L Mode Not Selected Output Disabled Read Write I/O Pin High-Z High-Z Dout High-Z Cycle -- -- Read Write Current ISB1, ISB2 ICCA ICCA ICCA
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating Power Supply Voltage Relative to VSS Voltage Relative to VSS for Any Pin Except VCC Output Current (per I/O) Power Dissipation Temperature Under Bias Operating Temperature Symbol VCC Vin, Vout Iout PD Tbias TA Value - 0.5 to + 7.0 - 0.5 to VCC + 0.5 20 1.0 - 10 to + 85 0 to + 70 Unit V V mA W C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high impedance circuits. This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.
Storage Temperature -- Plastic Tstg - 55 to + 150 C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 10%, TA = 0 to + 70C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage (Operating Voltage Range) Input High Voltage Input Low Voltage * VIL (min) = - 0.5 V dc; VIL (min) = - 2.0 V ac (pulse width 2.0 ns). Symbol VCC VIH VIL Min 4.5 2.2 - 0.5* Typ 5.0 -- -- Max 5.5 VCC + 0.3 0.8 Unit V V V
DC CHARACTERISTICS
Parameter Input Leakage Current (All Inputs, Vin = 0 to VCC) Output Leakage Current (E = VIH, Vout = 0 to VCC) Output Low Voltage (IOL = + 8.0 mA) Output High Voltage (IOH = - 4.0 mA) Symbol Ilkg(I) Ilkg(O) VOL VOH Min -- -- -- 2.4 Max 1.0 1.0 0.4 -- Unit A A V V
POWER SUPPLY CURRENTS
Parameter AC Active Supply Current (Iout = 0 mA, VCC = max) AC Standby Current (VCC = max, E = VIH, No other restrictions on other inputs) MCM6249-20: tAVAV = 20 ns MCM6249-25: tAVAV = 25 ns MCM6249-35: tAVAV = 35 ns MCM6249-20: tAVAV = 20 ns MCM6249-25: tAVAV = 25 ns MCM6249-35: tAVAV = 35 ns Symbol ICC Min -- -- -- -- -- -- -- Typ 175 160 145 50 40 35 10 Max 190 175 160 60 50 40 15 Unit mA
ISB1
mA
CMOS Standby Current (E VCC - 0.2 V, Vin VSS + 0.2 V or VCC - 0.2 V) (VCC = max, f = 0 MHz)
ISB2
mA
MCM6249 2
MOTOROLA FAST SRAM
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25C, Periodically Sampled Rather Than 100% Tested)
Parameter Input Capacitance Input/Output Capacitance All Inputs Except Clocks and DQs E, G, W DQ Symbol Cin Cck CI/O Typ 4 5 5 Max 6 8 8 Unit pF pF
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 10%, TA = 0 to + 70C, Unless Otherwise Noted)
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1a
READ CYCLE TIMING (See Note 1)
MCM6249-20 Parameter Read Cycle Time Address Access Time Enable Access Time Output Enable Access Time Output Hold from Address Change Enable Low to Output Active Output Enable Low to Output Active Enable High to Output High-Z Output Enable High to Output High-Z Power Up Time Power Down Time Symbol tAVAV tAVQV tELQV tGLQV tAXQX tELQX tGLQX tEHQZ tGHQZ tELICCH tEHICCL Min 20 -- -- -- 5 5 0 0 0 0 -- Max -- 20 20 6 -- -- -- 9 9 -- 20 MCM6249-25 Min 25 -- -- -- 5 5 0 0 0 0 -- Max -- 25 25 8 -- -- -- 10 10 -- 25 MCM6249-35 Min 35 -- -- -- 5 5 0 0 0 0 -- Max -- 35 35 10 -- -- -- 12 12 -- 35 Unit ns ns ns ns ns ns ns ns ns ns ns 5, 6, 7 5, 6, 7 5, 6, 7 5, 6, 7 4 Notes 2, 3
NOTES: 1. W is high for read cycle. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus con- tention conditions during read and write cycles. 3. All read cycle timings are referenced from the last valid address to the first transitioning address. 4. Addresses valid prior to or coincident with E going low/E going high. 5. At any given voltage and temperature, tEHQZ max tELQX min, and tGHQZ max tGLQX min, both for a given device and from device to device. 6. Transition is measured 500 mV from steady-state voltage with load of Figure 1b. 7. This parameter is sampled and not 100% tested. 8. Device is continuously selected (E VIL, G VIL).
t
t
TIMING LIMITS
+5V RL = 50 OUTPUT Z0 = 50 VL = 1.5 V OUTPUT 255 5 pF 480 The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time. On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time.
(a)
(b)
Figure 1. AC Test Loads
MOTOROLA FAST SRAM
MCM6249 3
READ CYCLE 1 (See Note 8)
tAVAV A (ADDRESS) tAXQX Q (DATA OUT) PREVIOUS DATA VALID tAVQV DATA VALID
READ CYCLE 2 (See Note)
tAVAV A (ADDRESS) tELQV E (CHIP ENABLE) tELQX G (OUTPUT ENABLE) tGLQX tAVQV tELICCH tGLQV DATA VALID tEHICCL tGHQZ tEHQZ
Q (DATA OUT)
HIGH-Z
SUPPLY CURRENT
ICC ISB
NOTE: Addresses valid prior to or coincident with E going low/E going high.
MCM6249 4
MOTOROLA FAST SRAM
WRITE CYCLE 1 (W Controlled, See Notes 1, 2, and 3)
MCM6249-20 Parameter Write Cycle Time Address Setup Time Address Valid to End of Write Write Pulse Width Data Valid to End of Write Data Hold Time Write Low to Data High-Z Write High to Output Active Write Recovery Time Symbol tAVAV tAVWL tAVWH tWLWH, tWLEH tDVWH tWHDX tWLQZ tWHQX tWHAX Min 20 0 15 15 10 0 0 5 0 Max -- -- -- -- -- -- 9 -- -- MCM6249-25 Min 25 0 17 17 10 0 0 5 0 Max -- -- -- -- -- -- 10 -- -- MCM6249-35 Min 35 0 20 20 15 0 0 5 0 Max -- -- -- -- -- -- 15 -- -- Unit ns ns ns ns ns ns ns ns ns 5,6,7 5,6,7 Notes 4
NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus con- tention conditions during read and write cycles. 3. If G goes low coincident with or after W goes low, the output will remain in a high-impedance state. 4. All write cycle timings are referenced from the last valid address to the first transitioning address. 5. Transition is measured 500 mV from steady-state voltage with load of Figure 1b. 6. This parameter is sampled and not 100% tested. 7. At any given voltage and temperature, tWLQZ max < tWHQX min both for a given device and from device to device.
WRITE CYCLE 1 (W Controlled, See Notes 1, 2, and 3)
tAVAV A (ADDRESS) tAVWH E (CHIP ENABLE) tWLWH tWLEH W (WRITE ENABLE) tAVWL D (DATA IN) tWLQZ Q (DATA OUT) HIGH-Z HIGH-Z tDVWH DATA VALID tWHQX tWHDX tWHAX
MOTOROLA FAST SRAM
MCM6249 5
WRITE CYCLE 2 (E Controlled, See Notes 1, 2, and 3)
MCM6249-20 Parameter Write Cycle Time Address Setup Time Address Valid to End of Write Enable Pulse Width Write Pulse Width Data Valid to End of Write Data Hold Time Write Recovery Time Symbol tAVAV tAVEL tAVEH tELEH, tELWH tWLEH tDVEH tEHDX tEHAX Min 20 0 15 15 15 10 0 0 Max -- -- -- -- -- -- -- -- MCM6249-25 Min 25 0 17 17 17 10 0 0 Max -- -- -- -- -- -- -- -- MCM6249-35 Min 35 0 20 20 20 15 0 0 Max -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns 5,6 Notes 4
NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus con- tention conditions during read and write cycles. 3. If G goes low coincident with or after W goes low, the output will remain in a high-impedance state. 4. All write cycle timing is referenced from the last valid address to the first transitioning address. 5. If E goes low coincident with or after W goes low, the output will remain in a high impedance condition. 6. If E goes high coincident with or before W goes high, the output will remain in a high impedance condition.
WRITE CYCLE 2 (E Controlled, See Notes 1, 2, and 3)
tAVAV A (ADDRESS) tAVEH tELEH E (CHIP ENABLE) tAVEL tWLEH W (WRITE ENABLE) tDVEH D (DATA IN) DATA VALID tEHDX Q (DATA OUT) HIGH-Z tELWH tEHAX
ORDERING INFORMATION
(Order by Full Part Number) MCM
Motorola Memory Prefix Part Number
6249
XX XX
XX
Shipping Method (R2 = Tape and Reel, Blank = Rails) Speed (20 = 20 ns, 25 = 25 ns, 35 = 35 ns) Package (WJ = 400 mil SOJ)
Full Part Numbers -- MCM6249WJ20 MCM6249WJ25 MCM6249WJ35
MCM6249WJ20R2 MCM6249WJ25R2 MCM6249WJ35R2
MCM6249 6
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
WJ PACKAGE 400 MIL SOJ CASE 857A-02
32
17
F N
32 PL
0.17 (0.007)
DETAIL Z
S
TB
S
A
S
1
16
0.17 (0.007) -AL G
S
D 32 PL T BS A
S
S
NOTE 3
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. TO BE DETERMINED AT PLANE -T-. 4. DIMENSION A & B DO NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 5. DIMENSION A & B INCLUDE MOLD MISMATCH AND ARE DETERMINED AT THE PARTING LINE. 6. 857A-01 IS OBSOLETE, NEW STANDARD 857A-02. MILLIMETERS MIN MAX 20.83 21.08 10.03 10.29 3.75 3.26 0.50 0.41 2.48 2.24 0.81 0.67 1.27 BSC 1.14 0.89 0.64 BSC 1.14 0.76 11.30 11.05 9.52 9.27 1.01 0.77 INCHES MIN MAX 0.820 0.830 0.395 0.405 0.128 0.148 0.016 0.020 0.088 0.098 0.026 0.032 0.050 BSC 0.035 0.045 0.025 BSC 0.030 0.045 0.435 0.445 0.365 0.375 0.030 0.040
P 0.17 (0.007) -B0.10 (0.004)
TA
S
B
S
E R 0.25 (0.010)
S
C
K
DETAIL Z
-T-
SEATING PLANE
S RADIUS TA
S
B
S
NOTE 3
DIM A B C D E F G K L N P R S
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 303-675-2140 or 1-800-441-2447 JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. 81-3-5487-8488
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MOTOROLA FAST SRAM
MCM6249/D MCM6249 7

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